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Start for FreeZeeshan Rafique
Cpu Verification Engineer @Semidynamics
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WORK HISTORY
Cpu Verification Engineer @Semidynamics
Barcelona, ES
Responsible of generating assembly test for new and existing features in the CPU.• Added new instructions and covergroups in Test generator, written in UVM. • Achieved 94% ISA coverage for RISC-V scalar Out-of-Order core.• Wrote a unit-level UVM test bench for complex instruction decoder module.• Contributing in top level test bench of CPU.• Wrote Python scripts to automate processes.• Added nightly and weekly regressions in CI.
EDUCATION
Usman Institute of Technology
Electrical Engineering, Computer Systems Engineering
ABOUT ZEESHAN RAFIQUE
Hardware Design & Verification Engineer with 5+ years of experience in SystemVerilog, RISC-V processor design, RISC-V Vector, Floating Point 754), microarchitecture, Out of Order execution, interconnects (AXI4, TileLink-UL, Wishbone), memory-mapped I/O (UART, SPI, QSPI, PWM), System-on-Chip communication, resource-efficient hardware implementation, Advance UVM, functional coverage, random instruction generation, assembly language, and automation with Python. As a RISC-V Ambassador, I have delivered several talks to promote and encourage the adoption of RISC-V in the local community. Additionally, I have trained and mentored more than 60 undergraduate students, helping them enter the semiconductor industry. Email: z••••••••@gmail.com GitHub: zeeshanrafique23
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