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Geancarlo Abich
Senior Cpu Performance Engineer @Semidynamics
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WORK HISTORY
Senior Cpu Performance Engineer @Semidynamics
Barcelona, ES
Development of reliable and automated performance modeling platforms and tools to enable analysis from core-level microarchitecture to SoC/MPSoC integration, optimizing decision-making across early, middle, and post-silicon phases of the product life cycle. Focused on enhancing RISC-V IP capabilities for AI workloads (Neural Networks, LLMs) in Edge and HPC environments.RISC-V Out-of-Order (OoO) microarchitecture analysisRISC-V tensor and vector optimizationRISC-V SIG Performance (Linux kernel PMU, trace, and profiling)RISC-V QEMU performance, profiling, and estimation assessmentPerformance modeling frameworks and workload evaluationVirtual Prototyping (SST, QEMU, gem5, SystemC, TLM2.0, C/C++)Testing, profiling, and automation (CI/CD) for AI and HPC applicationsDynamic Binary Instrumentation (DBI) for workload characterizationCoherency evaluation in multicore and MPSoC systemsHPC-AI communication (InfiniBand, IPoIB, RDMA, RoCE, Soft-RoCE, iWARP, and NFSoRDMA)FPGA-based prototyping and performance validationSilicon product performance, project, and reliability life cycle (early, middle, and post-silicon)
EDUCATION
Federal University of Rio Grande do Sul
Master of Science (MSc), Multiprocessor Embedded Systems Design
Universidade de Santa Cruz do Sul
Bachelor of Engineering (BEng), Computer Engineering
Federal University of Rio Grande do Sul
Doctor of Philosophy - PhD, Early soft error reliability assessment of Machine Learning models executing on IoT Edge devices
SKILLS
ABOUT GEANCARLO ABICH
I am a Senior CPU Performance Engineer focused on the development and orchestration of reliable and automated performance modeling frameworks that drive data-driven and/or performance efficiency design decisions throughout the semiconductor product life cycle. My expertise covers co-design from CPU cores to SoCs and MPSoCs, spanning early microarchitectural exploration, workload characterization and optimization, and post-silicon performance and power validation.I have collaborated with RISC-V performance task groups in the definition of performance monitoring standards and pioneered performance modeling tools for the Linux kernel, enabling advanced workload characterization and analysis. My work includes RISC-V out-of-order microarchitecture analysis, tensor and vector optimizations, workload-driven performance modeling, AI and HPC application profiling, dynamic binary instrumentation (DBI) for detailed workload characterization, coherency evaluation in multicore and MPSoC systems, and FPGA-based prototyping for rapid performance validation.I hold a Ph.D. in Microelectronics from UFRGS, Brazil, where my doctoral thesis was recognized with the E.J. McCluskey Best Doctoral Thesis Award, one of the most prestigious international awards in test technology. My research contributions led to a book published by Springer Nature and multiple peer-reviewed publications across journals and international conferences. Throughout my academic and professional career, I have collaborated with universities and industry partners in Europe and Latin America, bridging advanced research and industrial impact in processor IP and performance engineering. My research interests focus on exploring the trade-off between performance and reliability to achieve optimal design metrics, including PPA (Performance, Power, Area), PPW (Performance per Watt), and requirements for Safety-Critical and Mission-Critical performance trade-offs.More about my work:GitHub: https://github.com/mrgabich/Portfolio: https://drgabich.wixsite.com/drgabichUFRGS:
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