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Mohammed Eladawy
Verification Engineer @Semidynamics
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WORK HISTORY
Verification Engineer @Semidynamics
Barcelona, ES
EDUCATION
Ras Al Khaimah Secondary School
High School/Secondary Certificate Programs, Very good
Cairo University
Bachelor's degree, Electrical, Electronics and Communications Engineering, Good
Cairo University
Master's degree, Electrical, Electronics and Communications Engineering, (GPA 3.2/4.0)
ABOUT MOHAMMED ELADAWY
I got my BSc and MSc in Electronics and Electrical Communication Engineering from the Faculty of Engineering, Cairo University, 2011 and 2019, respectively.*+5 years of experience on digital design/verification and FPGA prototyping include- Transforming Matlab/C system model to efficiently synthesizable RTL code- Architecture design, RTL development, implementation and verification (functional and Gate Level Simulation verification), FSM, and multiple clock domain designs- Synthesizing, implementing, and solving static timing analysis problems using Xilinx FPGA design flow- Following up with frontend and backend team to resolve linting, synthesis, and implementing issues *+2 years of experience in verification include- SystemVerilog verification for assertion and Coverage - Building a UVM verification environment for direct and random test * my experience include- programming language ( Verilog, SystemVerilog, C/C++, MATLAB, UNIX shell scripting, MAKEFILE )-Tools ( MATLAB, Questasim, Xcellium, Synopsis VCS, Synopsis Verdi, Synopsis Design Compile and Xilinx Vivado, and, Xilinx SDK)*+10 years using Linux OS
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