Mehul Patel
Design Verification Engineer @Cirrus Logic
Chandler, AZ, US
EMAILS
m••••••••@cirrus.com
MOBILE NUMBERS
+14•••••••88
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WORK HISTORY
Feb 2023 — Present
Design Verification Engineer @Cirrus Logic
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SKILLS
SemiconductorsVhdlSystemverilogUvmLabviewVerification LanguagesAlteraSystem on a Chip (Soc)ModelsimCStatic Timing AnalysisSynopsys ToolsSpiLogic SynthesisSimulationsLadder LanguageField-Programmable Gate Arrays (Fpga)OopC++VerilogAssertion Based VerificationFunctional VerificationLogic DesignFpgaVcsApplication-Specific Integrated Circuits (Asic)LinuxMatlabOopsPerlAsicScadaI2cTesting
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