Mehul Patel
- Role
- Design Verification Engineer at Cirrus Logic
- Location
- Chandler, AZ, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Engineer
Feb 2023 — Present
Skills
- Semiconductors
- Vhdl
- Systemverilog
- Uvm
- Labview
- Verification Languages
- Altera
- System on a Chip (Soc)
- Modelsim
- C
- Static Timing Analysis
- Synopsys Tools
- Spi
- Logic Synthesis
- Simulations
- Ladder Language
- Field-Programmable Gate Arrays (Fpga)
- Oop
- C++
- Verilog
- Assertion Based Verification
- Functional Verification
- Logic Design
- Fpga
- Vcs
- Application-Specific Integrated Circuits (Asic)
- Linux
- Matlab
- Oops
- Perl
- Asic
- Scada
- I2c
- Testing
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