Ashkar Ali

Principal Engineer, Intel 18a Td Foundry Program, Intel Foundry @Intel

Portland, OR, US
EMAILS
a••••••••@intel.com
MOBILE NUMBERS
+13•••••••51

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WORK HISTORY

May 2025 — Present

Principal Engineer, Intel 18a Td Foundry Program, Intel Foundry @Intel

Hillsboro, OR, US

Lead technologist for Intel 18A, driving device analysis, PDK quality, PPA methodology, and silicon bring‑up across multiple customer programs- Partner with design, modeling, test, and customer teams to resolve silicon‑limiting issues and deliver predictable performance, power, and yield- Define product‑level performance and power expectations, translating customer requirements into actionable PDK and silicon‑validation targets- Develop methodologies (FoM cell PPA, automated SPICE flows) that accelerate design convergence and improve cross‑team decision‑making- Influence next‑generation node definitions (18A‑P, 14A) through data‑driven insights on PPA trade‑offs, design feedback, and silicon debug- Provide technical leadership across the organization, coaching engineers and delivering high‑visibility communications to senior leadership and customers.

EDUCATION

2007 — 2012

Penn State University

PhD, Electrical and Electronics Engineering

2003 — 2007

Indian Institute of Technology, Madras

BTech

SKILLS

Thin FilmsSemiconductorsJmpDevice EngineeringMatlabProcess IntegrationR&DLithographyDevice ModelingSimulationsResearch and Development (R&D)CharacterizationMaterials ScienceRfSemiconductor IndustryNanotechnologyVlsiCompound SemiconductorsCmosPhysicsDevice Characterization

ABOUT ASHKAR ALI

I’m a Principal Engineer with 13+ years building and enabling advanced‑node silicon across Intel 10nm, 7, 4, 18A/18A-P, and 14A. My work sits at the intersection of device physics, design enablement, and product execution — driving PDK quality, DTCO, PPA optimization, silicon bring‑up, and yield/debug for high‑performance compute and AI workloads.I lead cross‑functional programs from early modeling through high‑volume silicon, partnering with design, foundry, test, and customer teams to turn complex technology challenges into predictable performance, power, and yield outcomes. I’ve shaped node strategy, resolved silicon‑limiting issues across multiple customer programs, and delivered methodologies that accelerate design convergence and improve product quality.I’m motivated by hard problems, fast learning cycles, and building silicon that performs exactly the way customers need it to — from first power‑on to production‑ready maturity.

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