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Jaswinder Singh
Sr Staff Soc Emulation Models Debug Engineer @Intel
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WORK HISTORY
Sr Staff Soc Emulation Models Debug Engineer @Intel
Hillsboro, OR, US
Developed 10 empirical KPIs (By Collateral, By Model TTRC, By Model collateral fix TPT, By Team found, By Development phase, By environment, By domain, By Unique vs Known Bugs, By Severity/Impact, By Sighting 2 Bug Ratio)• Optimized debug throughput and time to root cause for emulation models, reducing debug cycle time by 25% through analyzing showstopper and high severity issues across 2 product lines, improving response time efficiency. • To streamline model development and debug processes, presently establishing closed loop learning to target accelerate future model iterations by 15% for 5 upcoming SoC projects.
EDUCATION
University of Phoenix. Arizona
Bachelor of Science
Babson F.W. Olin Graduate School of Business
Master of Business Administration
Self Paced Learning
R Language & Python
Government Polytechnic
Diploma
ABOUT JASWINDER SINGH
Multi dimensional 28 years experience in various leadership roles across Semiconductor industry - Individual engineering contributor, engineering program management, Strategic engineering operations management, financial engineering management and engineering management - Managed complex matrixed transformative corporate projects and excelled in strategic partnerships inside and outside Intel - Lead, mentor, and inspire a growing team of experienced engineers globally who are focused on improving automation effectiveness - Manage business relationships with senior leaders to understand their strategy, identify where our team can add value, and influence leaders towards long-term partnerships
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