Seenivasan M

About Seenivasan M

Overall 22 years of experience in VLSI industry# 18 years of hands on experience in RF & Analog Mixed Signal / IO/DDR Layout design# 2 Years of hands on experience in SoC Floorplan and Physical Verification domain# 2 years of VLSI Services company experience managing Analog and PD division.# Have work experience on various technologies starting from 120nm to 28nm, 14FF,10nm & 7FF# Hands on experience in layout of RF blocks like LNS, LDOs, Band gap, Buck and power management blocks, ET, amplifier etc.# Successfully Taped Out RF chip in 14nm.#Responsible for delivering Analog/Mixed Signal cores such as ADC, DAC, PLLs for both WTR & MSM Products.#Managed a team of 60+ people both in layout domain and SoC Floorplan and Physical Verification domain.# Have taken full responsibility in developing Input-Output (IO) buffer layout of various blocks like glitch filter, slew controlled buffer, and high speed analog IOs like Gen1, Gen2 and Gen3 DDRs.# Hands-on experience in developing full IO library starting from architecture definition, power bus design, floor planning, layout design and final delivery along with QA checks.#Hands on experience in developing ESD structures, custom IO cells like high speed analog tx and receivers.# Responsible for the team management, project management, project planning, milestone tracking, final hand off and QA# Sound knowledge of design concepts like layout matching, shielding, latch-up & ESD requirement, DFM, EM & IR analysis, current density requirement, power mesh etc.# Involved in resource planning and recruitment process, technical interview and mentoring# Good communication skill, Effective team player, management skills, Eager to learn new things and like to face challenges. Very approachable and hardworking.Specialties• Cadence Back-end tools, Virtuoso Layout Editor & XL, Virtuoso Analog Design Environment & Innovus.• Verification tools: Calibre LVS/DRC/ERC/PERC.• Programming languages: C• Scripting Languages: SKILL, Perl. Undergone two days workshop on \"Managing Technical People+\" offered by Blessing White

Experience

1. Director of Operations

   RAKIYA Information Technology Solution

   Dec 2023 — Present · Chennai, IN

Education

• Birla Institute of Technology and Science, Pilani

  Master of Science (M.S.), MicroElectronics

  2005 — 2007

• Kamaraj College of Engg and Tech

  Bachelor of Engineering (B.E.), Electronics and Communications Engineering

  1999 — 2003

Skills

• Floorplanning
• Debugging
• Project Management
• Esd Control
• Hands on Experience in Rf/Mixed Signal Layouts
• Experience in Writing Skill/Diva Scripts
• Hands on Experience in Io Layout
• Good Undertstading of Esd/Lup Concepts and Methods to Solve Them
• Perl
• Power Management
• Hands -on Experience in High Speed Ddr Layouts Both in Gen1 and Gen2
• Vlsi
• Asic
• Soc
• Analog
• C
• Virtuoso
• Cadence
• Vhdl