Nilesh Padhi
Senior Digital Design Engineer @Cirrus Logic
Signup · Get unlimited contacts
WORK HISTORY
Senior Digital Design Engineer @Cirrus Logic
Mesa, AZ, US
EDUCATION
SVKM's Narsee Monjee Institute of Management Studies (NMIMS)
Bachelor of Engineering (B.Eng.), Electronics and telecommunications Engineering
Arizona State University
Master's degree, Electrical Engineering
SKILLS
ABOUT NILESH PADHI
I am a Graduate Electrical Engineer, MSE with a specialization in CMOS VLSI Design and Signal Processing from Arizona State University, USA. I did my Bachelor\'s in Electronics and Telecommunication engineering from the SVKM’S NMIMS University, India.My core areas of interest lie in the domain of ASIC, Digital Signal Circuit design and VLSI hardware design. My academic projects have been focused on RTL Design & Synthesis projects. I have proficient knowledge in the domain of Signal & Image Processing, Computer Vision, Deep Learning and Machine learning.Computer Languages: C++, Assembly, System Verilog (UVM, Assertions, functional & Code Coverage), Perl, TCL, Python, MATLAB.Hardware Design tools: Cadence Virtuoso, Cadence Innovus, Synopsys (hspice, Design Compiler, IC Validator (DRC, LVS), StarRC, PrimeTime (STATIC TIMING ANALYSIS)), Calibre, SolidWorks, Questa, VManager, Spyglass LintVLSI Technology nodes: SAED 32nm PDK, ASAP7 (ASU 7nm PDK).Deep Learning and Computer Vision Packages: Keras, Pytorch, Scikit-learn, OpenCV (C++).DSPs Used: Freescale DSP56858, TI TMS320VC5510, XILINX FPGA NEXYS 2 BOARD.
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.