Mini Raina

Engineering Manager @Intel

Providing technical & non-technical leadership and managing multi-geo diverse custom layout teams with focus on • Planning scope and delivering single source industry-standard custom layout technology files on all Intel process nodes (3nm, 5nm, 7nm, 10nm, 22nm & beyond). Contribute to resource planning to ensure program success • Effectively communicate program statuses, identify potential risks and setbacks, and develop mitigation strategies. Manage communication within and between internal and external teams • Develop schedules, identify critical paths and bottlenecks, and maintain PDK execution throughout the duration of programs • Work cross-functionally to develop best practices for technology development processes in a quickly changing and dynamic environment to ensure on time delivery • Continuously improving specifications, test plans and automation to ensure high quality PDK collaterals and improve overall custom layout experience • Enable industry standard custom layout tools and collaterals to handle challenging advanced technology design rules and concepts for Test Chips, early PDKs, and DTCO activities • Providing excellent customer support with high quality training and documentation