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Start for FreePawan Agarwal
Rfic Design Manager @MaxLinear
San Jose, CA, US
EMAILS
p•••••••@marvell.com
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Jan 2022 — Present
Rfic Design Manager @MaxLinear
EDUCATION
N/A
Indian Institute of Technology, Madras
B. Tech & M.Tech, Electrical, Electronics, Communications, and Computer Engineering
N/A
Washington State University
PhD, Wireless systems and integrated circuits design
SKILLS
CmosAgilent AdsPllSerdesVlsiCadence VirtuosoAnalog Circuit DesignAnalogBicmosSimulationsMixed SignalMatlabSemiconductorsVerilog-a
ABOUT PAWAN AGARWAL
16+years of enjoying architecting a variety of RF, Analog, and Mixed-Signal circuits and systems using FinFet, SiGe, and GaN processes. Recently worked on 200/100G data center links, Docsis4.0 cable home networks, and mmW beamforming arrays.
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