Yong Chang
Staff Design Verification Engineer @Cirrus Logic
Edinburgh, GB
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MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Oct 2016 — Present
Staff Design Verification Engineer @Cirrus Logic
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Edinburgh, GB
SystemVerilog, UVM, SVA, Formal Verification, hardware-software co-sim, gate-level-simChip-level, IP-level, subsystem-level verificationCadence Xcelium, JasperGold, Synopsys Verdi,
EDUCATION
2001 — 2008
Chongqing University of Post and Telecommunications
Master of Technology - MTech
ABOUT YONG CHANG
ChipAgents SystemVerilog, UVM, OVM,VMM SystemVerilog Assertion, JasperGold Formal…
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