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Saptak Acharjee

Soc Physical Design, Staff Engineer @Samsung Semiconductor

Kolkata, WB, IN
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

May 2025 — Present

Soc Physical Design, Staff Engineer @Samsung Semiconductor

Bangalore, IN

EDUCATION

2017 — 2019

Indian Institute of Technology, Madras

Master of Technology - MTech, Microelectronics

ABOUT SAPTAK ACHARJEE

As a R&D Physical Design, Staff Engineer at Synopsys, I work with leading semiconductor companies to provide them with innovative and optimized solutions for their physical design challenges. I use my expertise in Synopsys tools and cutting edge technology solution to enable faster and more reliable design closure and verification. I have a strong background in VLSI and microelectronics, which I developed during my Master of Technology degree at the Indian Institute of Technology, Madras. I also have proficiency in Python, C, and C++, which I apply to implement machine learning algorithms for improving the efficiency and accuracy of physical design processes. I am passionate about learning new technologies and solving complex problems in the field of electronic design automation.

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