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Sandesh Shankarappa
Sr Manager Systems Design Engineering (Post-silicon Verification) @AMD
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WORK HISTORY
Sr Manager Systems Design Engineering (Post-silicon Verification) @AMD
Austin, TX, US
Senior Manager leading post-silicon IO functional validation for server-class SoCs.Owns PCIe (Gen5/Gen6) and CXL (2.0/3.0) bring-up, compliance, interoperability, and debug.Drives validation strategy, test content, automation, and lab infrastructure (exercisers/analyzers).Partners cross-functionally and mentors teams to accelerate root cause and time-to-market.
EDUCATION
Visvesvaraya Technological University
B.E., Electronics and Communication
University of Central Florida
M. S., Computer Engineering
SKILLS
ABOUT SANDESH SHANKARAPPA
Engineering leader with 15+ years of experience in semiconductor industry, leading end-to-end design, emulation, and validation for high-end server SoCs. Deep expertise across post-silicon validation, pre-silicon IP/SoC verification, emulation, system-level testing, and firmware development, with a track record of building high-performing teams and driving multi-vendor, multi-program execution. Known for translating project needs into reliable, high-performance solutions and improving bring-up/debug efficiency through robust methodologies.
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