Saisandhyarani Singanamala

WORK HISTORY

EDUCATION

ABOUT SAISANDHYARANI SINGANAMALA

Academic Summary:• Experience with multiple aspects of ASIC Design Flow such as Logic Design, System Verilog RTL Coding and Functional Verificationincluding Gate Level Simulations, Static Timing Analysis (STA) and Physical Design.• Experience in performing RTL Design for many digital circuits and dumped them onto Nexys4 DDR FPGA board and verifiedthe functionality.• Experience in working with Cadence Virtuoso Schematic and Layout tools and designed a library of all basic digital cells.• Self-Starter and Good at working independently or within a team.Educational Summary:• Pursuing Master’s in Electrical Engineering at California State University, Sacramento.GPA (So far): 3.8 (Expected graduation: December 2019)• Bachelor’s in engineering at Rajiv Gandhi University of Knowledge Technologies, INDIA.GPA: 3.6Technical Skills:Programming Languages: System Verilog, Verilog, VHDL, UVM, JAVA, Python, C, Perl Scripting, X86 Assembly Language ProgrammingSimulators: Synopsys VCS, Modelsim and SpectreTools: Cadence Virtuoso tools, Vivado, MATLABAcademic Experience:Asynchronous FIFO Design:• Successfully Designed, Validated and Synthesized a fully parameterized and modularized Asynchronous FIFO (128 entries and 32 bit) as a team leader of two member team project and made sure Functionality, Performance targets met the SPEC.• Drove the Micro architecture definition and wrote Specification that included FSMs, block diagrams and detailed descriptions for all the design modules.• As a part of my responsibility Designed Write pointer, Comparator, Synchronizers and Memory modules using Verilog HDL and enabled my teammate to be able to design Read pointer module and provided critical help in understanding the design.• Created Validation Testbench and wrote test cases including corner cases using Verilog HDL and Verified by using VCS simulator.• Developed Design Constraints and analyzed timing reports and improved the design target frequency.Arithmetic Logical Unit (ALU) Design• Designed an Arithmetic Logical Unit using Verilog RTL coding as well as drawn schematics & Layout as a group project.• Acted as a team leader who owned entire Verilog RTL coding and drawing Schematics & Layout for Multiplier and top level ALU and verified using Synopsys VCS Simulator. Also, helped other team member with Verilog coding and schematic design.• Made sure Pre- & Post Layout simulations are clean on Schematic netlist by using SPECTRE and Verified Transient responses.