Rashmi Basari

Fpga Verification Engineer @Intel

San Jose, CA, US

Spearheaded the development of UVM-based verification testbenches for FPGA-based networkaccelerators, focusing on protocols such as Ethernet, AXI4, and AXI-lite. Enhanced processingefficiency and optimized CPU resource allocation for customer-centric workloads by generatingdiverse stimulus, setting up the verification environment, and designing scoreboards to validate DUToutputs- Led verification planning, testbench architecture, and test case development for IPs including DMAsockets and PTP bridges, ensuring protocol compliance and robust validation for high-reliabilityapplications- Designed and implemented UVM-based unit-level environments to validate RTL designs with a focus on AXI4, AXI-lite, and Ethernet interfaces. This enabled early detection and resolution of functional issues, ensuring protocol adherence and high-quality design output- Implemented functional coverage models to capture critical design functionalities across AXI4 andEthernet protocols, tracking verification progress thoroughly and maximizing coverage for completedesign validation- Conducted performance testing and analysis of hardware designs, particularly around data transfer and latency metrics on AXI4 and Ethernet paths, identifying bottlenecks and proposing improvements to enhance design efficiency- Collaborated with cross-functional design teams to gather in-depth understanding of protocolspecifications and design requirements, developing comprehensive and targeted verification strategies to ensure reliability and performance.

B V B College of Engg. & Technology, HUBLI

Bachelor of Engineering, Instrumentation Technology

California State University-Sacramento

Master's degree, Electrical and Electronics Engineering