Raksha Mairpady
Systems Firmware Reliability Intern @Frore Systems
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WORK HISTORY
Systems Firmware Reliability Intern @Frore Systems
Milpitas, CA, US
Developing firmware to test low-level digital functional blocks • Testing and debugging firmware on FPGA and RTL simulation platforms • Developing bootloader modules for new MCU and digital chip bring-up • Understanding, analyzing, and improving components of the AirJet Drive System implementation • Collaborating closely with firmware and software teams to ensure system reliability
EDUCATION
Little Flower Public School - India
ICSE BOARD
RNS Institute of Technology - India
Bachelor of Technology - BTech, electronics and communication engineering
Portland State University
Master's in Electrical and Computer Engineering
ABOUT RAKSHA MAIRPADY
As a graduate student in Electrical and Computer Engineering at Portland State University, I am excited to bring my expertise in embedded systems, Design verification SOC, RTL design, Post silicon Validation, Computer Architecture, digital circuit design, and FPGA applications to real-world challenges. I am actively seeking full-time opportunities starting September 2025, where I can leverage my skills, deepen my knowledge, and make meaningful contributions to innovative projects.My academic background includes a Master of Science in Electrical and Computer Engineering from Portland State University, where I currently hold a 3.83 GPA, and a Bachelor\'s in Electronics and Communication Engineering from RNSIT. My industry experience spans significant roles, including a Post-Silicon Validation Internship at Advanced Micro Devices (AMD), where I specialize in BIOS validation for CPU server cores, focusing on system stability and performance testing.In my role as a Project Trainee at ISRO, I led a team to implement spectral pre-processing transform techniques for multispectral and hyperspectral image compression using VHDL and wavelet-based approaches. This project, awarded \"Best Project\" at Project Open House Expo-2023, demonstrated my proficiency in VHDL, C, and FPGA platforms like the using Libero IDE. Additionally, I developed a memory controller for SRAM within spacecraft onboard computers, supporting ISRO’s mission requirements for data storage and retrieval.I am skilled in C, VHDL, Verilog, System Verilog, UVM and Python, and have a strong command over tools like Vivado, Libero IDE, Questa Sim, and Multisim, with protocol experience in I2C, UART, SPI, and JTAG. My projects include developing an execution-driven MIPS-lite pipeline simulator, an IoT-enabled weather station, and an award-winning two-player Pong game using the Nexys A7 FPGA.In addition to my technical skills, I bring strong interpersonal, public speaking, and organizational abilities. I have demonstrated leadership in team settings and am known for my effective communication and active listening skills. My involvement in state-level parades and cultural events at ISRO, MYTRI, and ISAAC has honed my adaptability and dedication to teamwork.Driven by a passion for technology and innovation, I am eager to continue contributing to and learning from dynamic teams where I can apply my diverse skills and experiences.
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