Logan Nguyen Hammel

Digital Design Team Member @Siliconjackets

Atlanta, GA, US

Tape-out 1- Achieved successful tape-out of a 6-stage, base ISA RISC-V core with 4KB of DFFRAM using the SkyWater 130nm process- Designed and verified a GCD module using a finite state machine, developing SystemVerilog testbenches for functional coverage, debugging, and validation- Gained end-to-end ASIC flow experience from RTL design through tape-out, including synthesis, timing signoff, and integration using the Cadence toolchain- Integrated the completed RISC-V core with the Caravel chip harness, allowing for our core to be incorporated into a standardized SoC framework- Developed a Python script to analyze GBA and PBA timing reports, identifying paths with setup/hold violations.Tape-out 2- Designed a RISC-V Min/Max module by researching ISA requirements, creating a spec and test plan, and beginning RTL implementation with SystemVerilog testbenches, synthesis prototyping, and verification.

Georgia Institute of Technology

Bachelor of Engineering - BE, Computer Engineering