Joshua Thong

Digital Design Engineer @Siliconjackets

Atlanta, GA, US

Programmed FSM to implement the Euclidean GCD algorithm in SystemVerilog• modified testbench for FSM and tested using Synopsys Verdi achieving 97% DUT coverage• Synthesized RTL & analyzed effect of different floorplan utilizations on congestion, maximum clock speed, and timing failures• Designing VGA controller with custom graphics module to intake commands through AXI into SRAM and output onto a screen

Georgia Institute of Technology

Bachelor of Engineering - BE, Electrical and Electronics Engineering