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Igor Arsovski

VP Lpu Hardware @英伟达

Williston, VT, US
EMAILS
i••••••••@nvidia.com
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

Dec 2025 — Present

VP Lpu Hardware @英伟达

US

EDUCATION

1997 — 2001

University of Toronto

Bachelor of Applied Science (B.A.Sc.), Computer Engineering

2001 — 2003

University of Toronto

Master's, Electrical and Computer Engineering

SKILLS

Analog Circuit DesignSocDramRtl DesignIntegrated Circuit DesignMicroprocessorsProcessorsTclHigh Performance ComputingCmosVlsiWebsphere Process ServerApplication-Specific Integrated Circuits (Asic)Hardware ArchitecturePhysical DesignAsicSramCircuit DesignSemiconductorsLow-Power DesignStatic Timing AnalysisLogic DesignFunctional VerificationSignal IntegrityTiming ClosureDebuggingStatistical ModelingTcamVerilogEdaAsic Memory StrategyComputer Architecture

ABOUT IGOR ARSOVSKI

Hardware Architect and first-principles engineer with a track record of driving innovation across the best known AI, HPC, and networking ASICs, from initial architecture and technology co-optimization to debug and deployment. Leading HW-debug efforts on high-reliability ASICs, including SDC mitigation in AI data centers and reliability fails on HPC supercomputers used in top US banks.IBM Master Inventor with over 100 patents and more than 40 papers and presentations at premier conferences.Prior to Groq, Igor held key technical leadership roles at Google, Marvell, GlobalFoundries, and IBM, consistently delivering high-impact engineering solutions across the semiconductor industry

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