Hiren Ajay Khurana
Soc Logic Design Engineer @Intel
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WORK HISTORY
Soc Logic Design Engineer @Intel
Vancouver, BC, CA
Designed RTL to integrate an SoC Root of Trust IP in a sub-system, instantiated tech specific SRAMs, and generated basic timing constraints for synthesis done using Fusion Compiler.• Enabled early area and cell estimation by developing flows to generate the NDMs for 5nm and 18A SRAMs for reference libraries, using Library Compiler.• Designed and implemented a verification environment for a sub-system, created a UVC to handle the AXI and APB VIP virtual interfaces, and connected the UVC to the RTL using a bind interface.• Created a UVM sequence that implements the bring-up sequence using an AXI RAL Adapter and UVM Register Model to execute boot flow. • Helped debug and bring up the system-control and security cores in the compute sub-system on an SoC based on ARM Neoverse architecture.• Built a strong understanding of the ARM v8/v9 Architecture, AXI4 and CHI protocol.
EDUCATION
The University of British Columbia
Bachelor of Applied Science - BASc
DAV Public School, Nerul
Physics, Chemistry, Mathematics, Computer Science
ABOUT HIREN AJAY KHURANA
Heyo! I\'m a Computer Engineering graduate from UBC, driven by an immense passion for SoC development and verification. My curiosity extends to mastering the seamless integration of emerging technologies and innovative software development practices in the field of ASICs. Beyond the realm of technology, I\'m an enthusiastic Formula 1 aficionado, finding solace in the exhilarating world of racing. When the need arises, I embark on spontaneous drives accompanied by some music, using it as my ultimate de-stressing ritual.
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