Colton Koop

Soc Logic Design Engineer @Intel

Vancouver, BC, CA

Collaborate with architects, design, and verification engineers to define thorough, precise, and verifiable design requirements and micro-architectures for SoC subsystems including buffer management, interface converters, semaphore controllers, synchronization systems, and hardware-implemented linked-list utilities.• Develop synthesizable SystemVerilog RTL for key modules, emphasizing clean, maintainable, and verifiable designs validated with testbenches and waveform debugging in Synopsys Verdi.• Configure, generate, and integrate SRAMs, ROMs, and register files using industry-standard memory generation tools (Synopsys, TSMC, Intel Foundry); create supporting flows, utilities, and documentation to streamline memory usage across projects.• Implement and package ARM and Intel interface protocols (AXI, AXI-Stream, APB, CHI) into reusable RTL components, improving SoC design consistency and modularity across teams.• Work with Intel proprietary tools for register-collateral definition, Network-on-Chip (NoC) configuration, and RTL encryption and delivery flows using IP-XACT–style description formats.• Build and maintain productivity scripts in Python for RTL generation, filelist automation, and architecture-to-RTL stub creation, accelerating design iterations and verification readiness.• Actively contribute to team culture and engagement through event organization, clubs, and cross-team collaboration initiatives.

Simon Fraser University

Bachelor of Applied Science (Honours with Distinction), Engineering Science, Minor in Mathematics