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Anees Sutarwala

Senior Architect Rtl Verification Group @Synopsys Inc

Portland, OR, US
EMAILS
a••••••••@synopsys.com
MOBILE NUMBERS
+13•••••••30

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WORK HISTORY

Jun 2025 — Present

Senior Architect Rtl Verification Group @Synopsys Inc

EDUCATION

1997 — 2001

Indian Institute of Technology, Bombay

Bachelor Science, Engineering Physics

2004

Texas A&M University

Master's, Electrical Engineering

SKILLS

Machine LearningVerilogDebuggingAsicSocRtl VerificationSystemverilogPerlEdaRtlProcessorsUpfVlsiRepository ManagementLow Power Design

ABOUT ANEES SUTARWALA

Design automation engineer with a passion to create technological solutions for critical business needs. Recognized corporate expert in the field of automation, RTL verification and low power design methodologies with 8 publications/presentations in technical conferences. Proficiency in building and guiding small R&D teams (cross-geographies) to develop solutions for technically complex problems. Extensive experience in collaborating with CAD technology-vendors to define specifications and subsequently deploy their next generation products.Specialties: Microprocessor DFT, Silicon Debug, RTL Languages (System Verilog), RTL Simulators (VCS), Multiple Power Plane design, UPF, Perl and Shell scripting.

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