Yilkal Andualem Belay

Lead Design Engineer @Cadence

Nice, FR

EMAILS

[email protected]

MOBILE NUMBERS

+91 *********19

Reveal Contact Details

Signup · Get unlimited contacts

WORK HISTORY

Aug 2025 — Present

Lead Design Engineer @Cadence

View department →

Valbonne, FR

EDUCATION

2007 — 2012

Bahir Dar University

B.Sc. degree

2013 — 2015

Università degli Studi di Pavia

Master's degree

2015 — 2018

Università degli Studi di Pavia

PhD

SKILLS

MatlabData ConvertersAnalog Ic DesignPythonVerilog-aBasic Computer SkillsMicrosoft OfficeSignal ProcessingAnalog/Digital Communication SystemsResearchAdvanced Design System (Ads)SimulinkCoursesLecturingRf Ic DesignDigital Ic DesignCadenceC++ElectronicsModelingUniversity TeachingPrograming (C++,Java)Jmp (Data Analysis)Electrical Characterization (Experiments)Latex

ABOUT YILKAL ANDUALEM BELAY

Experience and skills- Integrated circuit design (analog/digital), electronics design - IC design design/simulation/extraction CAD tools (such as Cadence)- Semiconductor memories (SRAM, ROM, Register File, STT-MRAM, Resistive RAM ): circuit and device - Modeling and experimental characterization of semiconductor devices (STT-MRAM, Resistive RAM)- Programming and scripting (Matlab, Python, C++, Cadence, Verilog-A, shell scripts)- Academic Research (mainly on emerging nonvolatile memory technologies)

This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.