Vipin Jasoria
Senior Staff Engineer @Ayar Labs
Signup · Get unlimited contacts
WORK HISTORY
Senior Staff Engineer @Ayar Labs
San Francisco, CA, US
SystemVerilog (System Verilog), UVM ( Universal Verification Methodology), SystemVerilog Assertions, Functional Coverage, Code Coverage, Formal Verification, Test bench development, Scripting using Python.
EDUCATION
Southern Illinois University Edwardsville
Master of Science - MS, Electrical Engineering
Rajasthan Technical University
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
SKILLS
ABOUT VIPIN JASORIA
They said people like stories. So here’s mine. My journey began with connecting tiny jumper wires on a breadboard, writing my first Verilog description of a D flip-flop, and eventually designing a fully functional RISC microprocessor. That curiosity for circuits and electronics led me all the way to the United States, where I pursued my Master’s degree and deepened my passion for technology.Driven by a mindset to go the extra mile and stay ahead of the curve, I bring 7+ years of experience in Digital Design and Verification, working with industry leaders such as Google, SEL, and Qualcomm. My expertise spans Verilog, SystemVerilog, UVM, and RTL Verification across both ASIC/SoC and FPGA domains.Beyond engineering, I take pride in being a mentor and educator. During my master’s program at Southern Illinois University, I helped and mentored 150+ engineers, supporting their successful transitions across various engineering disciplines. I enjoy learning, teaching, and building meaningful professional connections.Thanks for stopping by—always happy to connect.My favorite quote in the world: “The day you become humble, is the day you become successful.”
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.