Vivek Trivedi

Associate VP Engineering @Astera Labs

Santa Clara, US

Responsible for all DFT and PD aspects for all Silicon programs at Astera Labs. Interface with vendors for all tools & flows, with TSMC for tapeouts, and implement our RTL2GDS flow. All aspects of DFT - SCAN, BIST, BSCAN and ATE bringup for all Astera ASIC products. Very much hands on, more focussed on mentoring and training young innovators. We are growing very rapidly, contact me if you would like to be a part of fast paced startup, and would like to learn and advance your technical career in ASIC design.

Indian Institute of Technology, Kanpur

BSEE, Electrical Engg

Stanford University

MSEE, Electrical Engg