Vishal Pindi
Design Verification Intern @Asicguru Ventures
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WORK HISTORY
Design Verification Intern @Asicguru Ventures
Noida, IN
I recently completed a project on the AMBA APB (Advanced Peripheral Bus) protocol, where I: Designed a synthesizable APB slave module with support for read/write operations Implemented a SystemVerilog testbench architecture including interface, driver, monitor, generator, scoreboard, environment, and test Verified protocol correctness for both wait and no-wait conditions Handled edge cases like invalid addresses, PSLVERR, and ensured proper handshaking (PSEL, PENABLE, PREADY)This experience strengthened my understanding of bus protocols, FSM design, and modular verification methodologies.
EDUCATION
Kakatiya University (University College of engineering and technology)
Bachelor of Technology - BTech
Dr B R Ambedkar National Institute of Technology, Jalandhar
Master of Technology - MTech
ABOUT VISHAL PINDI
Skilled in Digital Electronics | RTL Design | Functional VerificationI\'m passionate about digital design and verification, with hands-on experience in Verilog, SystemVerilog, and UVM. I enjoy building and debugging designs from scratch and ensuring their correctness through structured verification. Projects I’ve worked on include:1.APB Protocol (AMBA Bus Verification)2.Asynchronous and Synchronous FIFO (with overflow/underflow checking)3.RAM Memory Modules4.Traffic Light ControllerAll these were designed in Verilog and tested using SystemVerilog-based verification architectures, including drivers, monitors, and scoreboards. I\'m currently exploring high-speed protocols like AHB to deepen my understanding of bus-based SoC architectures. Previously at Accenture, I collaborated with a fantastic team on Spring Boot-based applications and contributed to backend stability by writing effective JUnit test cases. I’m now actively seeking opportunities in Design Verification, where I can apply my skills in RTL development, testbench architecture, and debugging, while continuing to learn and grow in the semiconductor/VLSI domain.Let’s connect if you\'re working in this space or have opportunities that align!#Verilog #SystemVerilog #UVM #DigitalDesign #DesignVerification #VLSI #RTL #EDA #SoC #Accenture #SpringBoot #JUnit
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