Vinayak Puradannavar
Internship Trainee @Vlsiguru Training Institute
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WORK HISTORY
Internship Trainee @Vlsiguru Training Institute
Bengaluru, IN
EDUCATION
K H Kabbur Institute of Technology Vidyagiri Dharwad
Diploma of Education, Electrical and Electronics Engineering
CESSJ High School Mishrikoti
SSLC
Vlsiguru Institute
Physical design
AGM Rural College of Engineering and Technology (AGMRCET)
Bachelor of Engineering - BE, Electrical and Electronics Engineering
ABOUT VINAYAK PURADANNAVAR
How do millions of gates come together to form a clean, timing-closed chip?This curiosity led me into the world of VLSI Physical Design and motivates me to learn every day.Hi, I’m Vinayak, a Physical Design Engineer (Fresher) trained in the complete RTL-to-GDSII flow. I have hands-on training experience on industry-standard tools, primarily Cadence Innovus, across multiple technology nodes (90 nm, 45 nm, 28 nm).My technical exposure includes:• Floorplanning & Power Planning• Timing-Driven Placement & Optimization• Clock Tree Synthesis (CTS) & Skew Optimization• Routing, DRC fixing & basic LVS awareness• MCMM Static Timing Analysis (STA) & ECO (Setup/Hold)During my training, I worked on resolving practical issues such as congestion, setup/hold violations, transition and capacitance violations, and clock imbalance using Innovus and PrimeTime.I am actively seeking entry-level opportunities in Physical Design / ASIC roles where I can apply my skills, continue learning, and contribute to high-quality silicon implementation.Location: Bengaluru | Open to relocationLet’s connect
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