Veerendra Budiredla
Trainee @Vlsiguru Training Institute
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WORK HISTORY
Trainee @Vlsiguru Training Institute
Bengaluru, IN
EDUCATION
Aditya College Of Engineering & Technology
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
ABOUT VEERENDRA BUDIREDLA
I am a 2025 graduate currently undergoing specialized training in the VLSI Physical Design domain, with a strong interest in ASIC implementation and backend design. My training focuses on both fundamental concepts and industry-relevant workflows used in modern chip design.I have built a solid foundation in Digital Design, CMOS basics, Linux, and TCL scripting, and I am gaining hands-on experience in Synopsys EDA tools. My exposure includes key Physical Design stages such as synthesis, floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and sign-off checks, following standard industry flows.I am actively developing my problem-solving and debugging skills while working with tools like Synopsys Design Compiler and ICC2. Training on Cadence tools is planned and will be taken up shortly to further strengthen my multi-tool expertise.As a motivated fresher, I am eager to apply my knowledge, learn from industry experts, and contribute to real-world VLSI projects in a challenging and growth-oriented environment.
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