Venkatesh Jaligam
Principal Engineer @Marvell Technology
Hyderabad, TG, IN
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MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Apr 2025 — Present
Principal Engineer @Marvell Technology
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Hyderabad, IN
CXL Memory Pooling, CXL Memory Expansion, CXL Near Memory
EDUCATION
2004 — 2006
CSNR Govt Junior College
Intermediate, Maths, Physics and Chemistry (M.P.C)
2007 — 2011
Princeton College of Engineering & Technology
B.Tech, Electrical, Electronics and Communications Engineering
2011 — 2012
Vector India, Inst, Hyderabad.
P.G Diploma in VLSI design.., Frond end and basics of Back end of VLSI.
2003 — 2004
ZPHS Raghunathpur
SSC, Maths and Science
SKILLS
Rtl DesignFunctional VerificationMicrocontrollersTclCadence VirtuosoRtl CodingCircuit DesignEdaVerilogImplementationCadenceLogic SynthesisChipscope ProVlsiPhysical DesignDebugging CodeSocXilinxSystemverilogStatic Timing AnalysisDigital ElectronicsTiming ClosureModelsimFpgaNcsimVhdlSimulationsAsicDebuggingXilinx Ise
ABOUT VENKATESH JALIGAM
Experienced Systems Design & Validation Engineer with a demonstrated history of working in the semiconductors industry.
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