Harish Kandpal
Senior Principal Cad Engineer @Marvell Technology
San Francisco, CA, US
EMAILS
h•••••••@marvell.com
MOBILE NUMBERS
+14•••••••20
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WORK HISTORY
Aug 2022 — Present
Senior Principal Cad Engineer @Marvell Technology
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Santa Clara, CA, US
EDUCATION
1996 — 1997
Indra Gandhi National Open University ( IGNOU )
Post Graduate Diploma
1990 — 1994
Institute of Engineering and Technology ( IET ), Lucknow University, Lucknow
B Tech
2008 — 2012
De Anza College
Project Management, programming, management
SKILLS
VerilogCadence VirtuosoVendor RelationshipsUnixTclSemiconductor Process TechnologyDebuggingPerlEdaLvsCadenceIcTestingDependable Team PlayerAlways Willing to LearnVirtuosoDrcIntegrated Circuits (Ic)Shell ScriptingCadence SkillSimulationsVlsiPositive Can-Do AttitudePhysical DesignVirtuoso Layout EditorMixed SignalPdk
ABOUT HARISH KANDPAL
20+ years EDA/VLSI + IT background with in depth knowledge in most areas of Cadence…
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