Venkata Sumanth Polineni
Design Verification Engineer @Vlsiguru Training Institute
Hyderabad, TG, IN
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Jan 2025 — Present
Design Verification Engineer @Vlsiguru Training Institute
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Bengaluru, IN
EDUCATION
2016 — 2020
GITAM Deemed University
Bachelor of Technology - BTech
ABOUT VENKATA SUMANTH POLINENI
Design Verification Trained Engineer @ VLSIGuru Training Institute || Digital Designs || Verilog || System Verilog || UVM || Functional Verification || Questa Sim || EDA playground || Debugging
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