Vaibhav Pawale
Design Engineer i @Cadence
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WORK HISTORY
Design Engineer i @Cadence
Pune, IN
EDUCATION
Vishwakarma Institute Of Technology
Bachelor's degree, Electronics and Communications Engineering
Jawahar Navodaya Vidyalaya - JNV
12th, CBSE
BITS Pilani Work Integrated Learning Programmes
Master of Technology - MTech, VLSI Design & Microelectronics
Jawahar Navodaya Vidyalaya - JNV
10th, CBSE
ABOUT VAIBHAV PAWALE
I’m a 2023 B.Tech Electronics & Telecommunications graduate from VIT Pune, working as a Physical Design Engineer in memory interface group at Cadence Design Systems. My expertise spans advanced nodes across major foundries: • Samsung: 4nm, 5nm • TSMC: 3nm • Intel: 1.8nm, 22nmPassionate about VLSI, digital/analog design, and signal processing, I aim to contribute to cutting-edge semiconductor innovations that push the limits of technology.
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