Tulasi Saisri Kavya

WORK HISTORY

EDUCATION

ABOUT TULASI SAISRI KAVYA

I completed my post-graduation from Gayathri Vidhya Parishad College Of Engineering in the stream of VLSI DESIGN AND EMBEDDED SYSTEMS. I successfully completed my internship course in DESIGN VERIFICATION at MAVEN SILICON from Bangalore. I\'m looking for a position with an organization where I can put my skills to use and contribute to its expansion, giving me the opportunity to grow professionally in the VLSI Front end domain. Here is a sneak preview of my knowledge. • Verilog • System Verilog • Universal Verification Methodology (UVM) • Digital electronics • Static Timing Analysis Project Experience • UVM Verification Environment for AHB-TO-APB Bridge project. • Router 1x3 Design and Verification. • Verification Plan for MOD10 Loadable up/down counter. • FPGA implementation of Angle of Arrival using Real-Time FMCW Radar • Constructed a combinational circuit using MUX, DECODER, LATCH, and Xilinx IP CORE, designed and implemented same on the FPGA Board. Tools Known • Xilinx Vivado • Xilinx ISE • Questa Sim • Synopsys VCS Personality traits • Patience • Organized • Adjustable • Easily mingle with everyone