Surbhi Bansal
Director of Design Engineering Dft @Cadence
Pune Division, MH, IN
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Jul 2025 — Present
Director of Design Engineering Dft @Cadence
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Pune, IN
EDUCATION
2001
DAV model school
XII
2001 — 2005
Netaji Subhas Institute of Technology
B.E., Electronics& Communication
SKILLS
TestingIcAsicBistSystem on a Chip (Soc)DebuggingSiliconDftSocSemiconductorsVerilogTest EngineeringVlsiJtagVery-Large-Scale Integration (Vlsi)Rtl DesignStatic Timing Analysis
ABOUT SURBHI BANSAL
Leading DFT activities on storage designs which includes defining test clock-reset structure, UDRs or any other test logic required, JTAG tap insertion, Boundary scan, Memory BIST insertion at RTL level. Defining scan chains and compression, test pin mux for all test modes, generating atpg patterns, bist patterns, bscan etc. Gate level simulation debug, silicon bringup and qual support.
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