Sujith P.
Principal Mts - Asic Fpga @Lyte
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WORK HISTORY
Principal Mts - Asic Fpga @Lyte
Mountain View, CA, US
Building foundation for Physical AI
EDUCATION
University of Florida
MS, Electrical and Computer Engineering
SKILLS
ABOUT SUJITH P.
10+ years of full-time experience in ASIC and FPGA design.1+ year of experience in academic research and as a student intern in ASIC, and FPGA-based design, RTL coding, low power design, design verification, linting, synthesis, CDC, LEC, Code coverage and lab debugging (FPGA Validation).Programming skills: System Verilog, Verilog, VHDL, C, C++, Python, PerlDevelopment tools: Vivado, Xilinx ISE, Synopsys Design Compiler, Novas Verdi, Conformal, Spyglass, Power Artist, Modelsim, Questa CDC, Quartus II, Cadence Design Suite (spectre), Cadence Virtuoso, Encounter, Matlab, Simulink, Ltspice Platforms: Windows, Linux, Unix
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