Suhas Shinde
Senior Analog Design Engineer @TDK
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WORK HISTORY
Senior Analog Design Engineer @TDK
Munich, DE
EDUCATION
VNIT(VRCE) Nagpur
M.Tech
VIT Pune
BE
ABOUT SUHAS SHINDE
PROFILEA motivated, enthusiastic Analog/High speed IC design engineer with +16 years of post graduate (M.Tech) experience with numerous patents and papers on credit. Strong understanding of Analog/High Speed IC designing, System level modeling and design issues, having worked in busy analog IC development and simulation environments with good customer interactions.Specialties: PLL, RF Synthesizers, BGR, LDO, Analogue Delay Line, Differential VCO, LVDS, CML Transceiver, Switched capacitor circuits, Biasing Circuit designs, Expertise on jitter budgeting/PN analysis for PLL, High speed transceivers. Recent Expertise: Automotive: LIN, GPIOs, Power System (BGR, LDOs), ESD, EMI/EMC, Power bridge, Gate driver design. Lab experience: Silicon evaluation of automotive chips.Papers:• Ultra-Low Power Current Reference Based on Flat Band Difference of MOSFETshttps://iopscience.iop.org/article/10.1088/17••••96/1729/1/012011• “BER Test Time Optimization” “Intel-22nm USB2 Squelch Yield Analysis & “Review of Oscillator Phase noise “PVT Insensitive Reference Current Paper “EOS Protection Circuit for USB2” • “MCML Muller-C Element with inductorless peaking” https://patentscope.wipo.int/search/en/detail.jsf?docId=WO20••••••70 • “Electronic method and system for delay compensation” “Charge injection and drain based electrical overstress (EOS) protection apparatus and method” http://patentscope.wipo.int/search/en/detail.jsf?docId=WO20••••••38 & recNum=11 & docAn=US20••••••29 & queryString=nano%20OR%20filter%20OR%20ceramic & maxRec=572847• “Driver Circuit\"(US11••••94B1). US11••••94B1 - Driver circuit - Google Patents
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