Sriharsha Inuganti

Senior Physical Design Engineer @Marvell Technology

Structural Design Block owner for Multiple Power Domain IP blocks used in Marvell’s 5G products- Successfully driven highly complex and timing challenged partitions from synthesis to tape-ins- Experienced working on designs operating at 2GHz and above on TSMC 7nm and 5nm technology nodes- Responsible for all aspects of physical design and implementation using synopsys and cadence tool suite- Proficient in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution and P&R, timing closure.