Siva Kumar Reddy Donthi Reddy

WORK HISTORY

EDUCATION

ABOUT SIVA KUMAR REDDY DONTHI REDDY

Having 14 years of experience in Big Die SoC and Sub System RDL, Bump Plan and Physical Verification, DDRPHY Physical Design and Memory Layout.Responsible for Big Die SoC, Sub System and Block level Physical Verification activities, RDL, IO plan and Blocks/Sub System integration in SoC in lower tech nodes.Physical Design Engineer worked on DDRPHY HM in TSMC (N4, N7P), Samsung( 4lpp, 5lpe, 8lpu,10lpe and 11lpe). Have experience on Floorplan, IR, Timing/Metal ECO\'s and PV->Interact with MSIP, DDRIO and ESD teams on the DDRPHY PD requirement and support them with quick feedback->Make FP for compact area without compromising on performance and PDN-> Plan strong PG mesh to avoid PDN issues and Totem RVDD and RVSS->Implement Timing ECO and Metal ECOs->Fix IR and EM issues->Fix all PV issues including DRC, LVS,ERC, PERC,ESD checks, DFM checks, etc. quickly->Work with Design and SoC teams to signoff PD/PV deliverables.SRAM/ROM Compiler and Semi Custom Memory Layout Engineer worked on TSMC (28nm, 16FF,N7P), GF (20nm), Samsung (14lpe,11lpp,10lpe,8lpu,7lpe and 5lpe)->Responsible for Leaf cell development from scratch till Top level->Provide inputs for Compiler code development and validate quickly to enable multiple configurations->Lead multiple projects in different technologies/foundries parallelly->Release the Memory Layout deliverables with high quality to SoC/HM teams->Interact with SoC team for any improvements or optimizations in Memory Layout->Guide the new team members for quick ramp up and productive in short span.