Sanjay Kakasaniya

WORK HISTORY

SKILLS

ABOUT SANJAY KAKASANIYA

Part of 2 successfull Chip tapout- Block Level TB development for Multi channel DMA engine using UVM methodology- Subsystem Level verification of PCIE System & USB2 system- Subsystem and Block level TB development and Verification of Interrupt Controller using UVM methodology- Block Level Verification of Universal Video interface unit(Transport Stream and HD/SD Video Capture/Render unit)- Block Level Verification of few PCIE RC features(Address translation unit, Memory Coherency Unit, Basic PCIE Memory transfers)- No timing full chip Gate Level Simulation and Best Case SDF GLS of PCIE, GPIO,I2C,SSI, UVI blocks- 8 and 16 channels DMA Block level verification using SV and VMM.Specialties: Hands on experience in System Verilog, UVMVery sharp RTL debugging skill and SoC verification skill