Choon Yap
Senior Principal Test Engineer @NXP Semiconductors
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WORK HISTORY
Senior Principal Test Engineer @NXP Semiconductors
Chandler, AZ, US
Test Lead (WT) and Team-Member (FT) of Universal-Analog-Front-End-IO devices (13-Bit DAC and 16 / 24-Bit ADC, low-drift VREF and offset buffers, high-precision amplifiers, HV input-protection-circuit and advanced diagnostic circuit for condition monitoring). Comprehend design data-sheet, devise solid test-plan, design WT probe card schematic and assigned IP blocks schematic of FT loadboard, devise test strategies and test-plan with efficient test-time and discuss with circuit-designers, product-engineering team to have required test coverage allocated, develop generic libraries (SPI, TRIM, SCAN, IDDQ, TMU + DIGCAP, NVM of both OTP and MTP, Search-SPEC, SARADC and TEMPERATURE_SENSOR) and complete AdvanTest 93K (SmartTest 7.5.4 and 7.6.6, C++) test-program with smartRDI engine to run production and characterization tests. Create Hardware-Checker solution to validate integrity of applied relays, capacitors and PMUX connections on the test-hardware. Supported Application and Customer-Engineering teams for NPI samples generation.
EDUCATION
Nanyang Technological University Singapore
Bachelor of Engineering (B.Eng.), Electrical and Electronics Engineering
Syracuse University
Master of Science - MS, Computer Science
SKILLS
ABOUT CHOON YAP
An experienced test development professional, major in developing both digital and mixed-signal Automated-Test-Equipment test solutions in the semiconductor industry. Capable to write test program and apply to Teradyne and AdvanTest test platforms. Proficient in Microsoft Visual C++, C#, Visual Basic, and Python Program Development, Management, Integrated Circuits (IC), Computer Interfacing Protocols (JTAG, SPI, I2C, UART).
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