Sandeep Rao Reddimalla

Design Verification Engineer @Abacus Semiconductor Corporation

Pacifica, CA, US

Verified System Verilog based hierarchical Memory Model and developed test-plan for various scenarios of write/read operations in UVM and ensured high quality of RTL design. Developed testcases in UVM for subsystems and SoC based on required specifications to verify debug IP connectivity and functionality. Debugged various regression test failures and performed integration of reusable IP testbench components into subsystems. Developed testcases for various inbound/outbound traffic scenarios randomizing message packet attributes. Working on RTL upgradation of existing HRAM subsystem’s LPDDR3 memory controller to support LPDDR5 configuration.

Montclair State University

Master's degree, Computer Engineering

Indian Institute of Technology (Indian School of Mines), Dhanbad

Bachelor's degree, Electrical, Electronics and Communications Engineering