Saideepak Reddy Mannem

Rtl Design and Verification Intern @Abacus Semiconductor Corporation

San Jose, CA, US
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WORK HISTORY

Jun 2025 — Present

Rtl Design and Verification Intern @Abacus Semiconductor Corporation

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San Jose, CA, US

EDUCATION

2015 — 2016

Sri Chaitanya high school

Tenth

2024 — 2025

San Jose State University

Master's degree

2019 — 2022

Sri Indu College Of Engineering & Technology

Bachelor of Technology - BTech

2016 — 2019

Government Polytechnic Yadagirigutta

Diploma of Education

ABOUT SAIDEEPAK REDDY MANNEM

I’m a driven Electrical and Computer Engineer with a strong foundation in RTL design, hardware validation, and functional verification. With hands-on experience across SMPS systems, embedded modules, and ASIC design flows, I bring a unique blend of hardware and verification skills to the table. My journey has taken me through board-level validation in the rail transit and power conversion industries, where I reduced EMI failures and improved system reliability through data-driven debugging and cross-functional collaboration. At the same time, I’ve built deep technical strength in SystemVerilog, UVM, and AMBA protocols, applying these to projects involving FIR filter accelerators, floating-point pipelines, and DDR memory schedulers.

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