Saikumar Galla

WORK HISTORY

EDUCATION

ABOUT SAIKUMAR GALLA

I’m a Design Verification Engineer with 2 years of hands-on experience across IP, subsystem, and SoC-level verification. I specialize in building UVM-based verification environments from scratch, developing test plans, and verifying complex digital designs with protocols like AXI, APB, and custom bus interfaces.I contributed to the verification of critical IPs like GPIO, TOG, AXI Write Coalesce, and LDPC-BCH subsystems. My expertise includes constrained-random verification, functional coverage, assertions, and reusable testbench components like scoreboards, monitors, and agents. Core Skills:• SystemVerilog | UVM | SVA• IP/Sub-System/SoC Level Verification• AXI, APB Protocols• Testbench Architecture• Functional Coverage & Assertions• Debugging & Waveform Analysis (Verdi, DVE)Always open to collaborating on challenging verification projects and pushing design quality to the next level.