Prajwal Gangur

Internship Trainee @Vlsiguru Training Institute

Proficient in designing digital systems using Hardware Description Languages (HDLs) such as Verilog and VHDL, encompassing the creation of combinational and sequential circuits, state machine comprehension, and logic design implementation.• Experienced in the complete design process for ASICs (Application-Specific Integrated Circuits) and FPGAs (Field-Programmable Gate Arrays), covering stages from Register Transfer Level (RTL) coding to GDSII, including synthesis, placement, routing, and optimization for power, area, and speed.• Skilled in ensuring design correctness through simulation and advanced verification methodologies like UVM (Universal Verification Methodology), adept at identifying and resolving functional errors prior to fabrication.• Knowledgeable in CMOS (Complementary Metal-Oxide-Semiconductor) technology, with expertise in physical design concepts such as layout, parasitics, and Design Rule Checks (DRC).• Familiar with semiconductor fabrication processes, including photolithography, and proficient in post-fabrication testing techniques to ensure chip functionality and address silicon-related issues.