Partho Chaudhuri
Senior Design Engineer @Xilinx
Hyderabad, TG, IN
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WORK HISTORY
Mar 2012 — Present
Senior Design Engineer @Xilinx
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Scan Architecture, RTL changes/writing, meet ATPG coverage targets.
EDUCATION
2000 — 2004
Nagpur University
B.E., Electronics
2004 — 2006
Indian Institute of Technology, Kharagpur
M.Tech.
SKILLS
Circuit DesignPhysical VerificationCmosDebuggingModelsimLogic SynthesisPcieDftComputer ArchitectureLow-Power DesignIcFormal VerificationAtpgLogic Design
ABOUT PARTHO CHAUDHURI
Senior Design Engineer at Xilinx
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