Nataraj Nagurthi
Lead Design Engineer @Cadence
Nizamabad, TG, IN
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+91 *********19
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WORK HISTORY
Apr 2024 — Present
Lead Design Engineer @Cadence
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Hyderabad, IN
Worked on DDR intel i18A Duty cycle Adjuster block functional simulation to meet the DC Range and DC_ERR with different layout extractions.Worked on DDR intel i18A ReadGate Serializer block characterization to meet Serializer DCD, Jitter, setup and hold. Did Monte-Carlo sims on clock gate block to meet DC, Jitter specs with random variation of 4.5σ
EDUCATION
2014 — 2018
CVR College of Engineering, Hyderabad
Bachelor of Technology - BTech
ABOUT NATARAJ NAGURTHI
Experienced Design Engineer with a demonstrated history of working in the semiconductors…
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