Mehdi Saeidi

WORK HISTORY

EDUCATION

ABOUT MEHDI SAEIDI

I\'m a SoC Design Engineer with hands-on experience in the full hardware development cycle—from architecture definition to RTL implementation, synthesis, and silicon bring-up. At MaxLinear, I’ve contributed to high-performance, low-power chips for data center and 5G applications, working closely with system architects, verification, and physical design teams. My background includes a Master’s in Electrical and Computer Engineering from UBC, where I focused on FPGA-based digital design and hardware acceleration. I\'m passionate about building efficient and scalable digital systems, with a strong focus on RTL design, low-power techniques, and system-level integration. Proficient in Verilog/SystemVerilog, C/C++, and Python, I’ve worked extensively with tools like Cadence Genus, Xcelium, and Synopsys DC. Whether it’s crafting microarchitecture or optimizing timing and power, I enjoy digging deep into the design to get things working—efficiently and correctly. I’m always looking to grow as a hardware designer and contribute to meaningful projects in cutting-edge SoC technologies.