Marzban Izad

WORK HISTORY

EDUCATION

ABOUT MARZBAN IZAD

I am an ASIC Digital Design Engineer with 5+ years of experience in RTL design, verification, and mixed-signal IC development, working extensively with Digital RTL Design, Simulation, Verification, STA, CDC, and Lint Analysis using industry-standard EDA tools (Synopsys Design Compiler, Cadence Genus, Innovus, PrimeTime, VCS, QuestaSim, etc.).In my previous role at Neuron IP, I develop and optimize high-speed digital modules for chiplet interconnects (UCIe, CXL, PCIe), create SystemVerilog analog block models to accelerate verification, and integrate a range of IPs—CPU cores (AHB interface), digital PHY, and AFE models. I also automate design workflows by leveraging Python for script generation (SystemVerilog shell scripts, Synopsys Design Constraints), register specification conversions (Excel to SystemRDL/IP-XACT), and multiple module instantiation.Beyond digital design, I have hands-on experience in integrated circuit design—spanning analog, digital, and mixed-signal systems at leading CMOS nodes such as GlobalFoundries 12nm, TSMC 65nm, 130nm, and 180nm. My M.Sc. research at the University of Alberta focused on ultra-low-power RF systems, resulting in an Transactions on Circuits and Systems I publication on non-iterative RF energy harvester design.By combining my ASIC digital design expertise with a strong commitment to innovation, I look forward to advancing next-generation semiconductor solutions and pushing the boundaries of chip-level integration.