Megha Goswami
Senior Dft Engineer Iii @NVIDIA
Bengaluru, KA, IN
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WORK HISTORY
Apr 2024 — Present
Senior Dft Engineer Iii @NVIDIA
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Bengaluru, IN
Gate level Scan insertion activities for data center chips and driving Methodology tasks to optimize flow execution efforts and deliver quality results for down-stream teams, and supporting internal cad based checks development and validation, working with CAD, Meth and VLSI teams.
EDUCATION
2004 — 2008
Madhav Institute of technology & Science, Gwalior M.P.
B.E., Electronics
2009 — 2011
BITS-Pilani
M.E., Microelectronics
SKILLS
ArmModelsimSocNcsimXilinxSystemverilogPhysical DesignDftFunctional VerificationDebuggingStatic Timing AnalysisFpgaAsicIntegrated Circuit DesignLogic DesignCTclVerilogCadence VirtuosoVlsiSemiconductorsRtl CodingRtl DesignTiming ClosureLogic SynthesisVhdlPerlEmbedded SystemsEda
ABOUT MEGHA GOSWAMI
DFT Engineer
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